The present invention generally relates to semiconductor integrated circuits, and more particularly to a semiconductor integrated circuit having a scan path circuit which uses a scan-in/out system.
Semiconductor technology has developed considerably over the recent years, and the integration density of semiconductor integrated circuits such as large scale integrated circuits (LSIs) and very large scale integrated circuits (VLSIs) has improved. Due to the increase in the integration density of the semiconductor integrated circuits, the number of terminals for data input/output has increased, and the number of input/output cells for data input/output has also increased. For this reason, it is impossible to secure the required number of input/output cells by the method of arranging the input/output cells only in a peripheral part of a chip of the semiconductor integrated circuit, and the input/output cells are now being arranged on the entire surface of the chip of the semiconductor integrated circuit. However, when the input/output cells are arranged on the entire surface of the chip, it is difficult to carry out a test which uses a prober.
On the other hand, as the integration density of the semiconductor integrated circuit increases, it becomes more and more difficult to make a diagnosis regarding whether or not the semiconductor integrated circuit operates as originally designed. As a result, there is a problem in that the cost involved in testing the semiconductor integrated circuit increases. Accordingly, there are demands to realize a semiconductor integrated circuit which can facilitate the test and reduce the cost involved in testing the semiconductor integrated circuit.
In the LSI production process, it is necessary to confirm the performance of the LSI. The test which is carried out to confirm the performance of the LSI can generally be divided into a test which is carried out at the development stage and a test which is carried out at the mass production stage. As the circuit test which is carried out at the mass production stage, there is a wafer probing test which is carried out at the end stage of the wafer process in order to reduce the defective chip mixture rate to the assembling process.
According to the wafer probing test, tip ends of needles 14 of the prober (not shown) make contact with corresponding pads 15 of input/output cells 11 which are arranged on an LSI chip 10 as shown in FIG. 1, and the electrical characteristics of the LSI chip 10 are checked by use of a signal generator, a waveform analyzer and the like which are coupled to the prober. As a result, it is possible to check not only the operation of the LSI chip 10 but also the transmission delay time, the rise time, the fall time and the like of signals. The LSI chip 10 which is found to be defective as a result of this wafer probing test is automatically marked as a defective chip and is excluded from the subsequent assembling process. Hence, the chips which are found to be defective after the assembling process are only those which are generated in the assembling process, and it is possible to considerably improve the production yield and production cost of the LSI.
Conventionally, the integration density of the LSI chip 10 is not extremely high and the number of input/output cells 11 is not extremely large. For this reason, the input/output cells 11 are provided at the outer peripheral end region of the LSI chip 10, that is, at the peripheral part of the LSI chip 10. Accordingly, it was sufficient to arrange the prober needles 14 which are required for the wafer probing test only at the peripheral part of the LSI chip 10.
But recently, due to the improved integration density of LSIs, it has become necessary to arrange the input/output cells for data input/output also at the inner part of the LSI chip. In order to carry out the wafer probing test similarly to the conventional case described above, it is necessary to arrange the prober needles 14 which are required for the wafer probing test so as to make contact with the pads 15 of all of the input/output cells 11 within an LSI chip 10A, as shown in FIG. 2. However, it is difficult to make a prober which has the prober needles 14 arranged to make contact with the pads 15 of all of the input/output cells 11 shown in FIG. 2, and even if were possible to make such a prober, there are problems in that the prober would become expensive and the contact accuracy of the prober needles 14 would become poor. In addition, the testing equipment must be provided with a large number of terminals for supplying the signals to all of the input/output cells 11, and there is a problem in that the cost of the testing equipment itself becomes high.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor integrated circuit in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a semiconductor integrated circuit comprising a semiconductor chip body, a plurality of input/output cells arranged on a surface of the semiconductor chip body at parts including a peripheral part and a central part of the semiconductor chip body, and at least an internal logic circuit provided on the semiconductor chip body, where each of the input/output cells include a pad and holding means coupled to the pad for holding incoming data, a plurality of the holding means are coupled in series in a test mode to form a scan path circuit, the input/output cell which has the pad for receiving an external test signal in a test mode is arranged at the peripheral part of the semiconductor chip body, and the test data held in the holding means of the input/output cell which is arranged at a part other than the peripheral part of the semiconductor chip body is transferred to the internal logic circuit in the test mode. According to the semiconductor integrated circuit of the present invention, it is possible to use a prober and a testing equipment which are similar to those conventionally used. Therefore, the prober needles can accurately contact the required pads and the testing can be carried out with ease using inexpensive prober and testing equipment which have simple constructions.
Still another object of the present invention is to provide the semiconductor integrated circuit of the type described above wherein predetermined ones of the input/output cells having the pads for receiving an external signal and outputting a signal outside the semiconductor integrated circuit are arranged in the peripheral part of the semiconductor chip body, and the holding means which are coupled to form the scan path circuit include a first shift register for shifting the test data which is received from the input/output cell having the pad for receiving the external test signal in the test mode. According to the semiconductor integrated circuit of the present invention, it is possible to test the semiconductor integrated circuit by simply contacting the prober needles to those pads which are arranged in the peripheral part of the semiconductor integrated circuit.
A further object of the present invention is to provide the semiconductor integrated circuit of the type described first, wherein predetermined ones of the input/output cells having the pads for receiving an external signal and outputting a signal outside the semiconductor integrated circuit are arranged in the peripheral part of the semiconductor chip body, first input/output cells are arranged in the peripheral part of the semiconductor chip body, second input/output cells are arranged in the central part of the semiconductor chip body, each first input/output cell is used for a data transfer between the semiconductor integrated circuit and another semiconductor integrated circuit which is independent from the semiconductor chip body, and each second input/output cell is primarily used for a data transfer within the semiconductor integrated circuit. According to the semiconductor integrated circuit of the present invention, it is possible to minimize the deterioration of the integration density of the internal logic circuit due to the provision of the input/output cells and effectively utilize the surface of the semiconductor chip body.
Another object of the present invention is to provide the semiconductor integrated circuit of the type described first, wherein the semiconductor chip body includes a substrate, and the semiconductor integrated circuit further comprises a pair of lower conductor layers formed on the substrate and coupled to mutually different logic circuits within the semiconductor integrated circuit, and an upper conductor layer which is formed on the pair of lower conductor layers to short-circuit the pair of lower conductor layers, where the upper conductor layer forms the pad of the input/output cell. According to the semiconductor integrated circuit of the present invention, no boundary scan chain is established if a conduction failure, a short-circuit and the like occurs within the pad or in a vicinity of the pad. Hence, it is unnecessary to contact the prober needles to all of the pads in order to test the conduction test and the like within the pad or in the region in the vicinity of the pad. As a result, as long as the bonding is possible, there is no other limits to reducing the intervals of the pads, and the pads can be arranged using an arbitrary layout which efficiently utilizes the surface of the semiconductor chip body. Therefore, the integration density of the semiconductor integrated circuit can be improved.
Still another object of the present invention is to provide a semiconductor integrated circuit comprising a semiconductor chip body, a plurality of input/output cells arranged on a surface of the semiconductor chip body, and at least an internal logic circuit provided on the semiconductor chip body, where the input/output cells include first input/output cells which are arranged in a peripheral part of the semiconductor chip body and second input/output cells which are arranged in a central part of the semiconductor chip body, each first input/output cell is used for a data transfer between the semiconductor integrated circuit and another semiconductor integrated circuit which is independent from the semiconductor chip body, and each second input/output cell is primarily used for a data transfer within the semiconductor integrated circuit. According to the semiconductor integrated circuit of the present invention, it is possible to minimize the deterioration of the integration density of the internal logic circuit due to the provision of the input/output cells and effectively utilize the surface of the semiconductor chip body.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.